parallel multiplier

Design and implementation of parallel multiplier used in the surround sound processing ASIC

环绕立体声处理ASIC中并行乘法器的设计与实现

By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used RS decoder is constructed.

采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。

A parallel multiplier configuration especially suitable for VLSI realization is presented.

用简化部分积的扩展符号位所在全加器的连接的方法提出了一种适于VLSI实现的并行乘法器结构。